Line edge roughness reduction compatible with trimming

ABSTRACT

A method and apparatus for reducing line edge roughness, comprising patterning a photoresist to define lines for etching an underlying layer, depositing a post development material between the lines, curing and removing the post development material to reduce line edge roughness, trimming the lines in the underlying layer, and then etching the underlying layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims benefit of U.S. Provisional Patent ApplicationSer. No. 60/640,504, filed Dec. 30, 2004, which is herein incorporatedby reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a method for fabricatingdevices on semiconductor substrates. More specifically, the presentinvention relates to a method for fabricating a gate structure of afield effect transistor.

2. Description of the Related Art

Ultra-large-scale integrated (ULSI) circuits typically include more thanone million transistors that are formed on a semiconductor substrate andcooperate to perform various functions within an electronic device. Suchtransistors may include complementary metal-oxide-semiconductor (CMOS)field effect transistors.

A CMOS transistor includes a gate structure that is disposed between asource region and a drain region defined in the semiconductor substrate.The gate structure generally comprises a gate electrode formed on a gatedielectric material. The gate electrode controls a flow of chargecarriers, beneath the gate dielectric, in a channel region that isformed between the drain and source regions, so as to turn thetransistor on or off. The channel and drain and source regions arecollectively referred to in the art as a “transistor junction”. There isa constant trend to reduce the dimensions of the transistor junctionand, as such, decrease the gate electrode width in order to facilitatean increase in the operational speed of such transistors.

In a CMOS transistor fabrication process, a lithographically patternedmask is used during etch and deposition processes to form the gateelectrode. However, as the dimensions of the transistor junctiondecrease (e.g., dimensions less than about 100 nm), it is difficult toaccurately define the gate electrode width using conventionallithographic techniques.

Therefore, there is a need in the art for a method of fabricating a gatestructure of a field effect transistor having reduced dimensions.

SUMMARY OF THE INVENTION

The present invention generally provides a method and an apparatus forreducing line edge roughness comprising patterning a photoresist todefine lines for etching an underlying layer, depositing a postdevelopment material between the lines, curing and removing the postdevelopment material to reduce line edge roughness, trimming the linesin the underlying layer, and then etching the underlying layer.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features of the presentinvention can be understood in detail, a more particular description ofthe invention, briefly summarized above, may be had by reference toembodiments, some of which are illustrated in the appended drawings. Itis to be noted, however, that the appended drawings illustrate onlytypical embodiments of this invention and are therefore not to beconsidered limiting of its scope, for the invention may admit to otherequally effective embodiments.

FIG. 1 depicts a flow diagram of a method of fabricating a gatestructure of a field effect transistor in accordance with the presentinvention.

FIGS. 2A-2J depict schematic, cross-sectional and top plan views of asubstrate having a gate structure being formed in accordance with themethod of FIG. 1.

To facilitate understanding, identical reference numerals have beenused, where possible, to designate identical elements that are common tothe figures.

It is to be noted, however, that the appended drawings illustrate onlyexemplary embodiments of this invention and are therefore not to beconsidered limiting of its scope, for the invention may admit to otherequally effective embodiments.

DETAILED DESCRIPTION

Embodiments of the present invention provide a method for fabricatingfeatures on a substrate having reduced dimensions. The features areformed by defining a first mask on regions of the substrate. The mask isdeposited on the substrate and then defined using lithographictechniques including use of a shrink resist and trimming to reduce lineedge roughness. The features are formed on the substrate by etchingportions of the substrate exposed by the mask.

The present invention is illustratively described with reference to amethod for fabricating a gate structure of a field effect transistor ona substrate. The gate structure comprises a gate electrode formed on agate dielectric layer. The gate structure is fabricated by depositing agate electrode layer on a gate dielectric layer over a plurality ofregions wherein transistor junctions are to be defined on the substrate.A underlying layer, such as a mask, is formed as described below onregions of the gate electrode layer between adjacent regions where thetransistor junctions are to be formed. The gate structure is completedby etching the gate electrode layer to the gate dielectric layer usingthe underlying layer.

The thickness of the mask conformably formed is used to determine thewidth of the gate electrodes of the transistors. The mask width dependson a deposition process, rather than on a lithography process,advantageously providing gate widths less than 30 nm.

FIG. 1 depicts a flow diagram of a process sequence 100 for fabricatinga gate electrode in accordance with the present invention. The sequence100 comprises process steps that are performed upon a gate electrodefilm-stack during fabrication of a field effect transistor (e.g., CMOStransistor).

FIGS. 2A-2J depict a sequence of schematic cross-sectional views (FIGS.2A-D, 2F-G, 2I-J) and top plan views (FIGS. 2E and 2H) of a substrateshowing a gate electrode being formed thereon using process sequence 100of FIG. 1. To best understand the invention, the reader shouldsimultaneously refer to FIGS. 1 and 2A-2J. The views in FIGS. 2A-2Jrelate to individual processing steps that are used to form the gateelectrode. Sub-processes and lithographic routines (e.g., exposure anddevelopment of photoresist, wafer cleaning procedures, and the like) arenot shown in FIG. 1 and FIGS. 2A-2J. The images in FIGS. 2A-2J are notdepicted to scale and are simplified for illustrative purposes.

Process sequence 100 begins at film stack formation step 102 (FIG. 1) byforming a gate electrode stack 202 on a wafer 200 (FIG. 2A).

The gate electrode stack 202 comprises a gate electrode layer 206 formedon a dielectric layer 204. The gate electrode layer 206 is formed, forexample, of doped polysilicon (Si) to a thickness of up to about 2000Angstroms. The dielectric layer 204 is formed, for example, of silicondioxide (SiO₂) to a thickness of about 20 to 60 Angstroms. The gatedielectric layer 204 may optionally consist of one or more layers ofmaterial such as, for example, silicon dioxide (SiO₂), hafnium silicondioxide (HfSiO₂) and aluminum oxide (Al₂O₃) to a thickness equivalent tothat of the single silicon dioxide (SiO₂) layer. It should beunderstood, however, that the gate electrode stack 202 may compriselayers formed from other materials or layers having differentthicknesses.

The layers that comprise the gate electrode stack 202 may be depositedusing a vacuum deposition technique such as atomic layer deposition(ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD),evaporation, and the like. Fabrication of the CMOS field effecttransistors may be performed using the respective processing modules ofCENTURA® platforms, ENDURA® platforms, and other semiconductor waferprocessing systems available from Applied Materials, Inc. of SantaClara, Calif.

At optional step 104 (FIG. 1), the process sequence continues bydepositing an optional hardmask 208 (FIG. 2B). The optional hardmask 208is preferably a dielectric anti-reflective coating (DARC) that issequentially formed on the gate electrode layer 206 (FIG. 2B). In oneillustrative embodiment, the optional hardmask 208 may comprise siliconoxynitride (SiON), silicon dioxide (SiO₂), or other material to athickness of about 100 to about 600 Angstroms. The optional hardmask 208functions to minimize the reflection of light during patterning steps.As feature sizes are reduced, inaccuracies in etch mask pattern transferprocesses can arise from optical limitations that are inherent to thelithographic process, such as light reflection. DARC depositiontechniques are described in commonly assigned U.S. Pat. No. 6,573,030,filed Jun. 8, 2000 and U.S. patent application Ser. No. 09/905,172 filedJul. 13, 2001, which are herein incorporated by reference.

Step 106 comprises preparing a photoresist (FIG. 1), and includesdepositing a photoresist (FIG. 2C) and developing the photoresist (FIG.2D). The photoresist layer 212 may be formed using any conventionaldeposition technique.

Step 106 is illustrated by FIGS. 2D and 2E. The photoresist is patternedby forming a patterned mask (e.g., photoresist mask) on the materiallayer beneath such a mask (i.e., underlying layer) and then etching thematerial layer using the patterned mask as an etch mask.

The patterned photoresists 212 are conventionally fabricated using alithographic process when a pattern of the feature to be formed isoptically transferred into the layer of photoresist. For example, thephotoresist is illuminated by UV light, a post-exposure bake at about130° C. is performed and unexposed portions of the photoresist areremoved by a developer, while the remaining photoresist retains thepattern.

Typically, the patterned photoresist comprises elements having the samecritical dimensions as the feature to be formed. However, opticallimitations of the lithographic process may not allow transferring adimensionally accurate image of a feature into the photoresist layerwhen a CD of the element is smaller than optical resolution of thelithographic process.

Step 106 results in rough lines as shown in FIG. 2E, a top view of thephotoresist 212 as shown in FIG. 2D. The sidewalls 261 of thephotoresist 212 have jagged edges as shown in FIG. 2E.

Next, a post develop layer is deposited during step 108 (FIG. 1). Ashrink resist layer 214 is deposited to engulf the patterenedphotoresist 212, for example, by spin coating. The thickness of theshrink resist layer is selected to be thick enough to engulf thephotoresist mask 212, but thin enough to cure properly. In someembodiments, 100 nm may be applied. A shrink resist layer may include aresin such aspoly(methyladamantyltrifluoromethacrylate(MAFMA)-norbornenehexafluoroisopropanol(NBHFA))and a photo acid generator such as triphenylsulfonium nonaflate. Thecomponents may be formulated and purchased from Fujifilm Arch Co., Ltd.Alternatively, Tokyo Ohka Kogyo, Lt. and Hitachi, Ltd. have developedSAFIER™ which also contains an acid and water soluble resin andadditives. Also, RELACS™ was developed by and is available for purchasefrom Clariant and Mitsubishi Electronics and is an aqueous polymer whichhas hydroxyl groups and a cross linking component.

Reducing line edge roughness of patterned photoresist step 110 isillustrated by FIGS. 2G and 2H. The shrink resist layer is cured bypreheating at 100° C. for about 20 to about 90 seconds, and then thebake temperature is raised to about 120 to about 150° C., preferablyabout 130 to about 140° C. The optional final shrinkage processtemperature was adjusted between 172 and 180° C. for 60 seconds.Generally, curing the shrink resist layer may be performed over 100-180°C. The sidewalls 262 of the photoresist mask 212 are smoothed andstraightened as the shrink resist layer is cured. Next, the substratesmay be rinsed with de-ionized water for about 20 to about 180 seconds,preferably 60 seconds to remove the residual shrink resist. Theresulting decrease in the jagged surfaces is illustrated by FIG. 2H. Theresulting line width can be larger than it was prior to the steps 108and 110.

The trimming photoresist step 112 is illustrated by FIG. 2I. In oneillustrative embodiment, the width of the mask 212 is trimmed using aplasma comprising hydrogen bromide (HBr) at a flow rate of 3 to 200sccm, oxygen at a flow rate of 5 to 100 sccm (corresponds to a HBr:O₂flow ratio ranging from 1:30 to 40:1), carbon tetrafluoride (CF₄), andargon (Ar) at a flow rate of 10 to 200 sccm. The plasma is generatedusing a plasma power of 200 to about 600 W and a bias power of 15 to 45W, a wafer pedestal temperature between 0 to 80° C. and a chamberpressure of about 2 to 30 mTorr. The trimming photoresist step 112 isperformed for about 20 to about 180 seconds.

One photoresist trimming process is performed using HBr at a flow rateof 80 sccm, O₂ at a flow rate of 28 sccm (i.e., a HBr:O₂ flow ratio ofabout 2.5:1), Ar at a flow rate of 20 sccm, a plasma power of 500 W, abias power of 0 W, and a wafer pedestal temperature of 65 degreesCelsius at a chamber pressure of 4 mTorr.

Etching hardmask and gate electrode layer step 116 is illustrated byFIG. 2J. At step 116, the pattern of the photoresist is transferredthrough the hard mask layer 208 and gate electrode layer 206. Duringstep 116 the mask layer 208 is etched using a fluorocarbon gas (e.g.,carbon tetrafluoride (CF₄), sulfur hexafluoride (SF₆), trifluoromethane(CHF₃), and difluoromethane (CH₂F₂)). Thereafter, the gate electrodelayer 206 is etched using an etch process that includes a gas (or gasmixture) comprising hydrogen bromide (HBr), oxygen (O₂), and at leastone inert gas, such as, for example, argon (Ar), helium (He), and neon(Ne). The terms “gas” and “gas mixture” are used interchangeably. In oneembodiment, step 116 uses the photoresist mask 212 as an etch mask andthe gate electrode layer 206 as an etch stop layer. Alternatively, anendpoint detection system of the etch reactor may monitor plasmaemissions at a particular wavelength to determine an end of the etchprocess. Further, both etch processes of step 116 may be performedin-situ (i.e., in the same etch reactor).

In one illustrative embodiment, the hardmask layer 208 comprisingsilicon oxynitride (SiON) is etched using carbon tetrafluoride (CF₄) ata flow rate of 40 to 200 sccm, argon (Ar) at a flow rate of 40 to 200sccm (i.e., a CF₄:Ar flow ratio of 1:5 to 5:1), plasma power of 250 W to750 W, bias power of 0 to 300 W, and maintaining the wafer pedestal at atemperature between 40 and 85° C. at a chamber pressure of 2 to 10mTorr. The hardmask layer 208 etch process is terminated by observingthe magnitude of the plasma emission spectrum at 3865 Angstroms, whichwill drop significantly after the underlying gate electrode layer 206 isreached, and subsequently conducting a 40 percent over etch (i.e.,continuing the etch process for 40 percent of the time that led up tothe observed change in the magnitude of the emission spectra).

One exemplary silicon oxynitride (SiON) hardmask layer 208 etch processis performed using carbon tetrafluoride (CF₄) at a flow rate of 120sccm, argon (Ar) at a flow rate of 120 sccm (i.e., a CF₄:Ar flow ratioof about 1:1), a plasma power of 360 W, a bias power of 60 W, a waferpedestal temperature of about 65° C., and a chamber pressure of 4 mTorr.

In one illustrative embodiment, the gate electrode layer 206 is etchedusing hydrogen bromide (HBr) at a flow rate of 20 to 100 sccm, oxygen(O₂) at a flow rate of 5 to 60 sccm (i.e., a HBr:O₂ flow ratio of 1:3 to20:1) argon (Ar) at a flow rate of 20 to 100 sccm, plasma power of 500 Wto 1500 W, bias power of 0 to 300 W, and maintaining the wafer pedestalat a temperature between 40 and 85 degrees Celsius at a chamber pressureof 2 to 10 mTorr. The gate electrode layer 206 etch process isterminated by observing the magnitude of the plasma emission spectrum at4835 Angstroms, and subsequently conducting a 30% over etch to removeresidues (i.e., continuing the etch process for 30% of the time that ledup to the observed change in the magnitude of the emission spectra).

One exemplary gate electrode layer 206 etch process is performed usinghydrogen bromide (HBr) at a flow rate of 60 sccm, oxygen (O₂) at a flowrate of 20 sccm (i.e., a HBr:O₂ flow ratio of about 3:1), Ar at a flowrate of 60 sccm, a plasma power of 600 W, a bias power of 100 W, a waferpedestal temperature of 65 degrees Celsius, and a pressure of 4 mTorr.Such process has etch directionality of at least 20:1. Herein the term“etch directionality” is used to describe a ratio of the etch rates atwhich the gate electrode layer 206 is removed on horizontal surfaces andon vertical surfaces, such as sidewalls 261. During step 110, the highetch directionality of the etch process protects the sidewalls 261 ofthe photoresist mask 212 and gate electrode layer 206 from lateraletching and, as such, preserves the dimensions thereof.

Also at step 116, the photoresist 212 is removed (or stripped) from thesubstrate (FIG. 2J). Generally, step 116 is performed using aconventional photoresist stripping process that uses an oxygen-basedchemistry, e.g., a gas mixture comprising oxygen and nitrogen. Duringstep 116, the etching chemistry and process parameters are specificallyselected to provide high etch directionality to preserve the dimensionsand location of the gate electrode layer 206. In one illustrativeembodiment, step 116 is performed in-situ using the DPS II module.

One exemplary photoresist stripping process is performed using hydrogenbromide (HBr) at a flow rate of 60 sccm, oxygen (O₂) at a flow rate of20 sccm (i.e., a HBr:O₂ flow ratio of about 3:1), argon (Ar) at a flowrate of 60 sccm, a plasma power of 600 W, a bias power of 100 W, a waferpedestal temperature of 65 degrees Celsius, and a chamber pressure of 4mTorr. The process has etch directionality of at least 10:1, as well asetch selectivity to the DARC film 208 (e.g., silicon oxynitride (SiON))over photoresist (mask 212) of at least 1:20.

EXAMPLE

In one exemplary process, bottom antireflective coating (BARC) is etchedwith 20 sccm HBr, 60 sccm CF₄, and 45 sccm oxygen at 4 mTorr with aplasma power of 400 W and bias of 60 W. The etch time at 19 W DC is 35seconds. The trim step is performed with the same properties as the BARCetch, except the bias is 30 W and the time is 20 seconds. In a followinghardmask etch step, a mixture of gases including 30 sccm SF₆, 35 sccmCH₂F₂, 45 sccm N₂, and 200 sccm He is introduced into a chamber at 4mTorr with a plasma power of 450 W and bias of 60 W at 11 W DC.

A soft landing is performed with 300 sccm HBr and 6.5 sccm O₂ at apressure of 6 mTorr. The plasma power is 400 W and the bias is 30 W witha DC of 11 W. An overetch step is performed with 300 sccm HBr, 20 sccmHeO₂, and 200 sccm He at 70 mTorr. The plasma power for the overetch is300 W, the bias is 30 W, and the DC is 19 W.

The invention may be practiced using other semiconductor waferprocessing systems wherein the processing parameters may be adjusted toachieve acceptable characteristics by those skilled in the arts byutilizing the teachings disclosed herein without departing from thespirit of the invention.

Although the forgoing discussion referred to fabrication of the fieldeffect transistor, fabrication of the other devices and structures usedin the integrated circuits can benefit from the invention.

While the foregoing is directed to embodiments of the present invention,other and further embodiments of the invention may be devised withoutdeparting from the basic scope thereof, and the scope thereof isdetermined by the claims that follow.

1. A method of reducing line edge roughness, comprising: patterning aphotoresist to form lines in the photoresist that define lines in anunderlying layer; depositing a post development material between thelines in the photoresist; curing and removing the post developmentmaterial to reduce line edge roughness; trimming the lines in thephotoresist; and then etching the underlying layer.
 2. The method ofclaim 1, wherein the post development material is a shrink resist. 3.The method of claim 1, wherein the underlying layer is a mask adjacent agate electrode.
 4. The method of claim 2, wherein the shrink resistcomprises poly(methyladamantyltrifluoromethacrylate(MAFMA)-norbornenehexafluoroisopropanol(NBHFA)).
 5. The method of claim 2, wherein the shrink resist is curedat a temperature of about 120 to about 150° C.
 6. The method of claim 5,wherein the shrink resist is cured for about 20 to about 180 seconds. 7.The method of claim 1, wherein the trimming the lines in the photoresistoccurs at a temperature of about 0 to about 80° C.
 8. The method ofclaim 7, wherein the trimming the lines in the photoresist occurs forabout 20 to about 180 seconds.
 9. The method of claim 1, whereinremoving the post development material occurs at a temperature of about0 to about 65° C. and atmospheric pressure.
 10. (canceled)
 11. A methodof reducing line edge roughness, comprising: patterning a photoresist todefine lines in the photoresist for etching an underlying layer, whereinthe underlying layer is a gate electrode; depositing a shrink resistbetween the lines; curing and removing the shrink resist to reduce lineedge roughness; trimming the lines in the photoresist; and then etchingthe underlying layer.
 12. The method of claim 11, wherein the shrinkresist comprises poly(methyladamantyltrifluoromethacrylate(MAFMA)-norbornenehexafluoroisopropanol(NBHFA)).13. The method of claim 11, wherein the shrink resist is cured at atemperature of about 120 to about 150° C.
 14. The method of claim 13,wherein the shrink resist is cured for about 20 to about 180 seconds.15. The method of claim 11, wherein the trimming the lines in thephotoresist occurs at a temperature of 0 to 80° C.
 16. The method ofclaim 15, wherein the trimming the lines in the photoresist occurs forabout 20 to about 180 seconds.
 17. The method of claim 11, whereinremoving the shrink resist occurs at a temperature of 0 to 65° C. 18.The method of claim 17, wherein the removing the shrink resist occursfor about 20 to about 180 seconds.